Introduction
to MIPS
MIPS or Microprocessor without Interlocked
Pileline Stages is a Reduced Instruction Set Computer (RISC)
instruction set architecture, meaning the CPU uses registers to perform
operations on.
A MIPS processor compose of an integer processing unit (the
CPU),and a collection of coprocessors that perform subsidiary tasks.
Microprocessor
Operations
Most processors will repeat three basic steps to execute one
machine instruction. The process of completing these steps is called a machine
cycle. Figure 1.1 shows the machine cycle.
Figure 1.1 A Machine cycle
Memory
Allocation
System based on MIPS processors is typically divide memory
into three parts:
I)
Text
segment: holds the machine language code for instructions in the source
file (user program).
II)
Data
segment: holds the data the program operates on. It is divided into two
parts:
Static data – contain
statically allocated data which its size does not change as the program access
them.
Dynamic data – It is on top of
static data. It is allocated and deallocated by the program executes.
III)
Stack
segment - It resides st the top of
the user address space. In a high level language
program,
local variables and parameters are pushed and popped on the stack as the
operating systems expands and shrink the shrink the stack segment toward the
data segment.
Data Alignment
Table 1.1 shows list data sizes apply to MIPS chips.
|
Type
|
Size(Binary)
|
Size(Hexadecimal)
|
|
Byte
|
8 bits
e.g. 10100011
|
2 bits
e.g. 3A
|
|
Word
|
4 bytes, 32 bits
e.g. 10000000……
|
8 bits
e.g. 12345ABC
|
|
Double Word
|
8 bytes,64 bits
e.g. 10000000……
|
16 bits
e.g. 123456789ABCDEF0
|
Table 1.1 MIPS Data Sizes
Table 1.2 shows data alignment in MIPS.
|
Double
|
|||||||
|
Word
|
Word
|
||||||
|
HalfWord
|
HalfWord
|
HalfWord
|
HalfWord
|
||||
|
Byte
|
Byte
|
Byte
|
Byte
|
Byte
|
Byte
|
Byte
|
Byte
|
Table 1.2 Data
Alignment
Registers
Registers are memory just
like RAM, except registers are much smaller and faster than RAM. In MIPS
the CPU can only do operations on registers,
and special immediate values.
MIPS processors have 32 general purpose registers that are numbered as
0-31 and another 32 floating-point registers, but some of these are reserved. A
fair number of registers however are available for your use. For example, one
of these registers, the program counter, contains the memory address of
the next instruction to be executed. As the processor executes the instruction,
the program counter is incremented, and the next memory address is fetched,
executed, and so on.
Registers all begin with
a dollar-symbol ($). The floating point
registers are named $f0, $f1, ..., $f31. The general-purpose registers have
both names and numbers, and are listed in Table 1.3 below. When programming in
MIPS assembly, it is usually best to use the register names.
|
Register
Number
|
Register
Name
(Mnemonic
Name)
|
Comments/Usage
|
|
$0
|
$zero
|
Always zero
|
|
$1
|
$at
|
Assembler Temporary(Reserved for assembler)
|
|
$2, $3
|
$v0, $v1
|
First and second return values, respectively
|
|
$4, ..., $7
|
$a0, ..., $a3
|
First four arguments to functions
|
|
$8, ..., $15
|
$t0, ..., $t7
|
Temporary registers (not preserved across a
function call)
|
|
$16, ..., $23
|
$s0, ..., $s7
|
Saved registers (preserved across a function
call)
|
|
$24, $25
|
$t8, $t9
|
More temporary registers
|
|
$26, $27
|
$k0, $k1
|
Reserved for kernel (operating system)
|
|
$28
|
$gp
|
Global pointer (preserved on call)
|
|
$29
|
$sp
|
Stack pointer (preserved on call)
|
|
$30
|
$fp
|
Frame pointer (preserved on call)
|
|
$31
|
$ra
|
Return address (automatically used in some
instructions)
|
Table 1.3 MIPS register conventions
Explanations:
-The zero
register ($zero or $0) always contains a value of 0. It is built
into the hardware and therefore cannot be modified.
-The $at
(Assembler Temporary) register is used for temporary values within
pseudo commands. It is not preserved across function calls.
- The $v
Registers are used for returning values from functions. They are not
preserved across function calls.
- The $a
registers are used for passing arguments to functions. They are not
preserved across function calls.
- The $t
(temporary registers) registers are caller-saved registers that are
used to hold temporary values .For a beginner; user can use these registers in
their program.
- The $s
(Saved Temporary) are callee-saved registers that used to store
longer lasting values. They are preserved across function calls. For a
beginner, user can use these registers in their program.
-The $k
registers are reserved for use by the operating system kernel.
- Global Pointer ($gp) is a pointer that points to the middle of a 64k block
of memory in the static data segment.
- Stack Pointer ($sp) – It points the last location on the stack and used to
store the value of the stack pointer.
Frame Pointer ($fp) - Used to store the value of the frame pointer.
Return Address ($ra) - Contains the return address written by jal (the
location in the program that a function needs to return to).
All Pointer Registers are preserved across
function calls.
Ø
SPIM simulate two coprocessors. Coprocessor 0
handles traps, exceptions, and the virtual memory system. SPIM simulates most
of the first two and entirely omits details of the memory system. Coprocessor 1
is the floating point unit. SPIM simulates most aspects of this unit.
Ø
Furthermore, Coprocessors 0 contains exception
control registers that handles exceptions. SPIM does not implement all of
coprocessors 0’s registers, since they are not much useful in a simulator or
part of the memory system, which is not implemented. However, it does provide
trap registers in Table 1.4.
|
Register Name
|
Register Number
|
Usage
|
|
BadVAddr
|
8
|
Memory address at which address exception occurred
|
|
Status
|
12
|
Interrupt mask and enable bits
|
|
Cause
|
13
|
Exception type and pending interrupt bits
|
|
EPC
|
14
|
Address of instruction that caused exception
|
Table 1.4 Trap Register
These registers are part of
coprocessor 0’s register set accessed by the mfc0 and mtc0 instructions.
15
8
4 1 0
|
|
Interrupt Mask
|
|
U
M
|
|
E
L
|
I
E
|
Figure 1.2
Status Register
|
B
D
|
|
Pending Interrupt
|
|
Exception Code
|
|
Figure 1.3
Cause Register
Figure 1.2
shows the bits in the Status register that are implemented by SPIM. The
interrupt mask holds a bit for each of the eight interrupt levels. If a bit is
one, interrupts at that level are allowed. If the bit is zero, interrupts at
that level are disabled. The user mode(UM) bit is 0 if the program was running
in kernel mode and 1 if it was running in user mode. The exception level (EL)
bit is commonly 0, but will set to 1 if an exception occurs. If the interrupt
enable (IE) it is 1, interrupts are allowed. If it is 0, they are disabled.
Figure 1.3
shows the bits in the Cause register. The eight pending interrupt bits
correspond to the eight levels. A bit becomes 1 when an interrupt at its level
has occurred but has not been serviced. The exception code bits contain a code
from Table 1.5 describing the cause of an exception.
|
Number
|
Name
|
Cause
of exception
|
|
0
|
Int
|
Interrupt (hardware)
|
|
4
|
AdEL
|
Address error exception (load or instruction fetch)
|
|
5
|
AdES
|
Address error exception (store)
|
|
6
|
IBE
|
Bus error on instruction fetch
|
|
7
|
DBUS
|
Bus error on data load or store
|
|
8
|
SYSCALL
|
Syscall exception
|
|
9
|
BKPT
|
Breakpoint exception
|
|
10
|
RI
|
Reserved instruction exception
|
|
12
|
OVF
|
Arithmetic overflow exception
|
|
13
|
Tr
|
Trap
|
Table 1.5
Exception code register
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