MIPS(R-Format/ I-Format/ J-Format) by CHEOK LI LI B031310127

A. MIPS INSTRUCTIONS FORMAT

There are three types of instruction format :

1. Register Type ( R-Type )

2. Immediate Type ( I-Type )

3. Jump Type ( J-Type )                                                 

A.1. Register Type ( R-Type )

R-Type instructions refer to register type instructions . The R-Type is the most complex among the three formats .

Below is the format of the R-Type instruction ( when it is encode in machine code ) :

Explaination of each of the field of the R-Type instruction :

ü 

op is short for "operation code" . The op is a binary encoding for the instruction and are seen in all ISAs . In MIPS, there is an op for add . The op in MIPS ISA is only 6 bits . Ordinarily , this means there are only 64 possible instructions . Even for a RISC ISA , which typically has few instructions , 64 is quite small .

This is the first source register . The source register is the regieter that holds one of the arguments of the operation .

This is the second source register .

This is the destination register . The destination register is the register where the result of the operation is stored .

The amount of bits to shift . Used in shift instructions .

An additional 6 bits used to specify the operation , in addition to the op .

A.2. Immediate Type ( I-Type )

This group includes instructions with an immediate operand , branch instructions ,and load and store instructions . All opcodes except 000000 , 00001x and 0100xx are used for I-Type instructions .

Below is the format of the R-Type instruction :

 

A.3. Jump Type ( J-Type )

This group consists of the two direct jump instructions , there are j and jal . J-type instructions use opcodes 00001x .

B. INSTRUCTION TYPE APPLICATIONS

a. Instruction Type : Non-Jump , R-Type

Example : add rd , rs , rt

Type : R

Instruction Coding :

ALU usage :

1. PC update : No update beyond the normal increment

2. Source operand fetch : rs and rt

3. ALU operation : Is determined by the function ( fn )

                                  field                                  

4. Memory access : -

5. Register write : The result from the ALU is written to

                                 rd .

b. Instruction Type : Jump Register

Example : jalr rd , rs

Type : R

Instruction Coding :

 

 

ALU usage :

1. PC update : No update beyond the normal increment

2. Source operand fetch : rs and rt

3. ALU operation : Is determined by the function ( fn )   

     field

4. Memory access : -

5. Register write : The result from the ALU is written to

     rd .

c. Instruction Type : Immediate

Example : addi rt , rs , imm

Type : I

Instruction Coding :

ALU usage :

1. PC update : No update beyond the normal increment

2. Source operand fetch : rs and immediate field

Ø  For all instructions except sltiu , the immediate field is sign extended . For sltiu , the immediate field is zero extended .

3. ALU operation : Is determined by the opcode

4. Memory access : -

5. Register write : The result from the ALU is written to

     rt .

d. Instruction Type : Branch

Example : beq $rs , $rt , imm

Type : I

Instruction Coding :

ALU usage :

1. PC update : If the branch condition is true , PCPC + 4

     + ( signed-extended immediate field ) << 2 .

2. Source operand fetch : rs and rt

3. ALU operation : The source operands are subtracted

     for comparison .

4. Memory access : -

5. Register write : -

d. Instruction Type : Load

Example : lw rt , imm ( rs )

Type : I

Instruction Coding :

ALU usage :

1. PC update : No update beyond the normal increment

2. Source operand fetch : rs and the sign extended

     immediate field

3. ALU operation : The two source operands are added

     to get the memory address .

4. Memory access : A memory read control signal is sent 

     to memory . The result from the ALU is sent to

     memory as the address .

5. Register write : The data from memory is written to rt .